2 papers
cs.AR2007
Synchronization Processor Synthesis for Latency Insensitive Systems
Pierre Bomel, Eric Martin, Emmanuel Boutillon
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni…
cs.AR2006
High-level synthesis under I/O Timing and Memory constraints
Philippe Coussy, Gwenolé Corre, Pierre Bomel +2
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper…