2 papers
cs.AR2026
EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis
Phat Tieu, Sayanti Jana, Matthew DeLorenzo +5
Modern chip design relies on electronic design automation (EDA) tools that generate large, heterogeneous artifacts, including source files, scripts, logs, netlists, and reports. An…
cs.AI2025
Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs
Sam Bush, Matthew DeLorenzo, Phat Tieu +1
Limitations in Large Language Model (LLM) capabilities for hardware design tasks, such as generating functional Verilog codes, have motivated various fine-tuning optimizations util…