most citedCompact Modeling of 0.35 micron SOI CMOS Technology Node for 4 K DC Operation using Verilog-A

2 citations · 2 across the 1 of their papers we have counts for

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cond-mat.mtrl-sci2010★ 2 cited

Compact Modeling of 0.35 micron SOI CMOS Technology Node for 4 K DC Operation using Verilog-A

A. Akturk, K. Eng, J. Hamlet +7

Compact modeling of MOSFETs from a 0.35 micron SOI technology node operating at 4 K is presented. The Verilog-A language is used to modify device equations for BSIM models and more…