6 citations · 11 across the 3 of their papers we have counts for
3 papers
Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock
Rourab Paul, Hemanta Dey, Amlan Chakrabarti +1
RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffing (PKRS) process is introduced between KSA and PRGA. It can also be made significantly faster if RC4 b…
Design space exploration for image processing architectures on FPGA targets
Chandrajit Pal, Avik Kotal, Asit Samanta +2
Due to the emergence of embedded applications in image and video processing, communication and cryptography, improvement of pictorial information for better human perception like d…
A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication
Rourab Paul, Sangeet Saha, Jkm Sadique Uz Zaman +3
In the field of cryptography till date the 1-byte in 1-clock is the best known RC4 hardware design [1], while the 1-byte in 3clocks is the best known implementation [2,3]. The desi…