6 citations · 6 across the 1 of their papers we have counts for
2 papers
cs.OH2013
Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit
Dipankar Saha, Subhramita Basak, Sagar Mukherjee +2
A modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with…
cs.AR2013★ 6 cited
A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme
Dipankar Saha, Subhramita Basak, Sagar Mukherjee +1
This paper proposes a Low-Power, Energy Efficient 4-bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power…