6 papers
On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies
Yanxin Zhang, Shayne Wadle, Yuxuan Xiong +3
Machine-learning predictors estimate processor performance far faster than cycle-level simulation. For design-space exploration, however, the valuable test is not merely reproducin…
Beyond Static Policies: Dynamic Selection Among Modern Microarchitectural Policies
Yanxin Zhang, Ian McDougall, Junnan Li +3
Modern processors gain performance from interacting policies: prefetchers, predictors, replacement rules, and schedulers. These policies are often evaluated one at a time, yet a po…
Beyond Static Policies: Exploring Dynamic Policy Selection for Single-Thread Performance Optimization
Yanxin Zhang, Ian McDougall, Junnan Li +3
For over a decade, processor design has focused on implementing sophisticated policies for various components of the out-of-order pipeline, including cache replacement and prefetch…
NeuroScalar: A Deep Learning Framework for Fast, Accurate, and In-the-Wild Cycle-Level Performance Prediction
Shayne Wadle, Yanxin Zhang, Vikas Singh +1
The evaluation of new microprocessor designs is constrained by slow, cycle-accurate simulators that rely on unrepresentative benchmark traces. This paper introduces a novel deep le…
SAHM: State-Aware Heterogeneous Multicore for Single-Thread Performance
Shayne Wadle, Karthikeyan Sankaralingam
Improving single-thread performance remains a critical challenge in modern processor design, as conventional approaches such as deeper speculation, wider pipelines, and complex out…
IPU: Flexible Hardware Introspection Units
Ian McDougall, Shayne Wadle, Harish Batchu +1
Modern chip designs are increasingly complex, making it difficult for developers to glean meaningful insights about hardware behavior while real workloads are running. Hardware int…