most citedLayout decomposition for triple patterning lithography

93 citations · 220 across the 5 of their papers we have counts for

collaborators

5 papers

cs.AR2014

Lithography Hotspot Detection and Mitigation in Nanometer VLSI

Jhih-Rong Gao, Bei Yu, David Z. Pan

With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithograp…

cs.AR2014★ 84 cited

EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation

Duo Ding, Bei Yu, Joydeep Ghosh +1

In this paper we present EPIC, an efficient and effective predictor for IC manufacturing hotspots in deep sub-wavelength lithography. EPIC proposes a unified framework to combine d…

cs.AR2014★ 38 cited

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing

Duo Ding, Bei Yu, David Z. Pan

In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Div…

cs.AR2014★ 5 cited

A High-Performance Triple Patterning Layout Decomposer with Balanced Density

Bei Yu, Yen-Hung Lin, Gerard Luk-Pat +3

Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high perfor…

cs.AR2014★ 93 cited

Layout decomposition for triple patterning lithography

Bei Yu, Kun Yuan, Boyang Zhang +2

As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) is a possible 193nm extension along the paradigm of double patterning lithography (D…