6 papers
CellE: Automated Standard Cell Library Extension via Equality Saturation
Yi Ren, Yukun Wang, Xiang Meng +6
Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal meth…
Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization
Yi Ren, Baokang Peng, Chenhao Xue +6
With the diminishing return from Moore's Law, system-technology co-optimization (STCO) has emerged as a promising approach to sustain the scaling trends in the VLSI industry. By br…
AC-Refiner: Efficient Arithmetic Circuit Optimization Using Conditional Diffusion Models
Chenhao Xue, Kezhi Li, Jiaxing Zhang +7
Arithmetic circuits, such as adders and multipliers, are fundamental components of digital systems, directly impacting the performance, power efficiency, and area footprint. Howeve…
Design Optimization of Flip FET Standard Cells with Dual-sided Pins for Ultimate Scaling
Rui Gui, Haoran Lu, Jiacheng Sun +7
Recently, we proposed a novel transistor architecture for 3D stacked FETs called Flip FET (FFET), featuring N/P transistors back-to-back stacked and dual-sided interconnects. With…
DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization
Yi Ren, Chenhao Xue, Jiaxing Zhang +5
The proliferation of deep learning accelerators calls for efficient and cost-effective hardware design solutions, where parameterized modular hardware generator and electronic desi…
DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators
Chenhao Xue, Yi Ren, Jinwei Zhou +6
Multipliers and multiply-accumulators (MACs) are fundamental building blocks for compute-intensive applications such as artificial intelligence. With the diminishing returns of Moo…