2 papers
cs.AR2026
Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System
Connor Rudy Sullivan, Amin Mamandipoor, Cole Ridge Strickler +1
Modern multicore system-on-chips (SoCs) share off-chip DRAM across cores, where bank-level interference can significantly degrade performance and threaten real-time guarantees. Whi…
cs.AR2025
Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems
Connor Sullivan, Alex Manley, Mohammad Alian +1
Modern commercial-off-the-shelf (COTS) multicore processors have advanced memory hierarchies that enhance memory-level parallelism (MLP), which is crucial for high performance. To…