collaborators

9 papers

cs.ET2026

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation

Xiaohan Jiang, Zeyu Li, Wei Zhang +1

The rapid development of photonic integrated circuits (PICs) is shifting the design flow from traditional graphical user interface (GUI)-based methods to script-based methods for h…

cs.AR2026

VersaQ-3D: Architecture Support for Visual Geometry Grounded Transformers via Versatile Quantization

Yipu Zhang, Jintao Cheng, Xingyu Liu +8

The paper introduces VersaQ-3D, a co-designed quantization algorithm and reconfigurable accelerator that enables low‑bit (4‑bit) inference of Visual Geometry Grounded Transformers…

cs.AR2026

FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs

Jiawei Liang, Haotong Qin, Linfeng Du +7

Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable…

cs.AR2026

HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing

Ya Wang, Hanwei Fan, Zhenguo Liu +4

Modern processor verification struggles to reach deep architectural states due to the inefficiencies of traditional mutation-based fuzzing. We propose HiFuzz, a novel hierarchical…

cs.PL2026

NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures

Shangkun Li, Jinming Ge, Diyuan Tao +6

Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising and versatile accelerator platform, offering a balance between the performance and efficiency of specialized acc…

cs.AR2025

FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration

Xingyu Liu, Jiawei Liang, Linfeng Du +5

In this work, we present FLEX, an FPGA-CPU accelerator for mixed-cell-height legalization tasks. We address challenges from the following perspectives. First, we optimize the task…