most citedAccelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock

2 citations · 2 across the 1 of their papers we have counts for

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1 paper

stat.AP2016★ 2 cited

Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock

Rourab Paul, Hemanta Dey, Amlan Chakrabarti +1

RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffing (PKRS) process is introduced between KSA and PRGA. It can also be made significantly faster if RC4 b…