most citedEquivalence Checking in Embedded Systems Design Verification using PRES+ model

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cs.LO2010★ 2 cited

Equivalence Checking in Embedded Systems Design Verification using PRES+ model

Soumyadip Bandyopadhyay

In this paper we focus on some aspects related to modeling and formal verification of embedded systems. Many models have been proposed to represent embedded systems. These models e…