7 papers
LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power
Wenkai Li, Yuchao Wu, Ziyan Guo +4
Accurate power analysis is critical in VLSI design, as it directly impacts power optimization strategies. However, traditional approaches are often hindered by the substantial runt…
RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
Ziyan Guo, Wenji Fang, Wenkai Li +3
Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive field…
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
Wenji Fang, Jing Wang, Yao Lu +4
Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI…
ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning
Yugao Zhu, Zhicheng Guo, Yuchao Wu +3
Hypergraph partitioning is a critical step in the design of complex embedded systems, essential for optimizing task mapping on heterogeneous MPSoCs and enabling multi-FPGA prototyp…
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
Jing Wang, Shang Liu, Wenji Fang +3
LLM-based RTL generation and reasoning is a promising direction for hardware design automation. High-quality benchmarks are critical infrastructure for tracking progress in this di…
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
Yuchao Wu, Wenji Fang, Jing Wang +3
Assertion-based verification (ABV) is a cornerstone of modern hardware design, yet manually translating design intent into formal SystemVerilog Assertions (SVAs) remains labor-inte…