2 papers
cs.AR2026
From Indiscriminate to Targeted: Functionally Critical Signal-Driven Assertion Generation using LLMs for Efficient RTL Verification
Yonghao Wang, Hongqin Lyu, Boling Chen +9
Functional verification has become the most time-consuming phase in IC development, and Assertion-Based Verification (ABV) is key to reducing debugging time. However, existing LLM-…
cs.AR2025
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
Jiaping Tang, Jianan Mu, Silin Liu +8
As intelligent computing devices increasingly integrate into human life, ensuring the functional safety of the corresponding electronic chips becomes more critical. A key metric fo…