5 papers
From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
Jie Zhang, Jiapeng Guan, Hao Zhou +4
Block Floating-Point (BFP) is emerging as an attractive data format for edge Neural Processing Units (NPUs), combining wide dynamic range with high hardware efficiency. However, it…
Strix: Re-thinking NPU Reliability from a System Perspective
Jiapeng Guan, Jie Zhang, Hao Zhou +8
DNNs and LLMs increasingly rely on hardware accelerators, including in safety-critical domains, while technology scaling and growing model complexity make hardware faults more freq…
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
Dean You, Jieyu Jiang, Xiaoxuan Wang +9
Runahead execution is a technique to mask memory latency caused by irregular memory accesses. By pre-executing the application code during occurrences of long-latency operations an…
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Tinglue Wang, Yiming Li, Wei Tang +6
Reliability and real-time responsiveness in safety-critical systems have traditionally been achieved using error detection mechanisms, such as LockStep, which require pre-configure…
NVR: Vector Runahead on NPUs for Sparse Memory Access
Hui Wang, Zhengpeng Zhao, Jing Wang +11
Deep Neural Networks are increasingly leveraging sparsity to reduce the scaling up of model parameter size. However, reducing wall-clock time through sparsity and pruning remains c…