3 papers
cs.AR2026
CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations
Yonghao Wang, Yang Yin, Hongqin Lyu +8
LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We pro…
cs.AR2025
AssertFix: Empowering Automated Assertion Fix via Large Language Models
Hongqin Lyu, Yunlin Du, Yonghao Wang +3
Assertion-based verification (ABV) is critical in ensuring that register-transfer level (RTL) designs conform to their functional specifications. SystemVerilog Assertions (SVA) eff…
cs.AR2025
AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging
Hongqin Lyu, Yonghao Wang, Yunlin Du +5
Assertion-based verification (ABV) serves as a crucial technique for ensuring that register-transfer level (RTL) designs adhere to their specifications. While Large Language Model…