2 papers
cs.AR2026
Automated SVA Generation with LLMs
Lik Tung Fu, Qihang Wang, Shaokai Ren +4
Functional verification remains a dominant cost in modern IC development, and SystemVerilog Assertions (SVAs) are critical for simulation-based monitoring and formal property check…
cs.AR2025
Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists
Haohang Xu, Chengjie Liu, Qihang Wang +10
Large Language Model (LLM) exhibits great potential in designing of analog integrated circuits (IC) because of its excellence in abstraction and generalization for knowledge. Howev…