5 papers
Programmable Packet Scheduling with Dynamic Reordering at Line Rate
Zekun Wang, Binghao Yue, Yichen Deng +3
High-speed switch packet scheduling demands both line-rate performance and programmability. Existing programmable hardware scheduling models, such as PIFO and PIEO, can express a b…
A Grouped Sorting Queue Supporting Dynamic Updates for Timer Management in High-Speed Network Interface Cards
Zekun Wang, Binghao Yue, Weitao Pan +2
With the hardware offloading of network functions, network interface cards (NICs) undertake massive stateful, high-precision, and high-throughput tasks, where timers serve as a cri…
RELIC-GNN: Efficient State Registers Identification with Graph Neural Network for Reverse Engineering
Weitao Pan, Meng Dong, Zhiliang Qiu +3
Reverse engineering of gate-level netlist is critical for Hardware Trojans detection and Design Piracy counteracting. The primary task of gate-level reverse engineering is to separ…
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures
Yingjie Qi, Jianlei Yang, Rubing Yang +5
Compute-in-memory (CIM) has emerged as a pivotal direction for accelerating workloads in the field of machine learning, such as Deep Neural Networks (DNNs). However, the effective…
Design of a Timer Queue Supporting Dynamic Update Operations
Zekun Wang, Binghao Yue, Weitao Pan +2
Large-scale timers are ubiquitous in network processing, including flow table entry expiration control in software defined network (SDN) switches, MAC address aging in Ethernet bri…