3 papers
cs.AR2026
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
Lik Tung Fu, Jie Zhou, Shaokai Ren +6
Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced sim…
cs.ET2026
RTLocating: Intent-aware RTL Localization for Hardware Design Iteration
Changwen Xing, Yanfeng Lu, Lei Qi +5
Industrial chip development is inherently iterative, favoring localized, intent-driven updates over rewriting RTL from scratch. Yet most LLM-Aided Hardware Design (LAD) work focuse…
cs.AI2025
ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications
Changwen Xing, SamZaak Wong, Xinlai Wan +9
While Large Language Models (LLMs) demonstrate immense potential for automating integrated circuit (IC) development, their practical deployment is fundamentally limited by restrict…