4 papers
Fleet: Hierarchical Task-based Abstraction for Megakernels on Multi-Die GPUs
Sangeeta Chowdhary, Ryan Swann, Sean Siddens +7
Modern GPUs adopt chiplet-based designs with multiple private cache hierarchies, but current programming models (CUDA/HIP) expose a flat execution hierarchy that cannot express chi…
Memory DisOrder: Memory Re-orderings as a Timerless Side-channel
Sean Siddens, Sanya Srivastava, Reese Levine +2
To improve efficiency, nearly all parallel processing units (CPUs and GPUs) implement relaxed memory models in which memory operations may be re-ordered, i.e., executed out-of-orde…
tritonBLAS: Triton-based Analytical Approach for GEMM Kernel Parameter Selection
Ryan Swann, Muhammad Osama, Xiaohu Guo +8
We present tritonBLAS, a fast and deterministic analytical model that uses architectural parameters like the cache hierarchy, and relative code and data placement to generate perfo…
HipKittens: Fast and Furious AMD Kernels
William Hu, Drew Wadsworth, Sean Siddens +6
AMD GPUs offer state-of-the-art compute and memory bandwidth; however, peak performance AMD kernels are written in raw assembly. To address the difficulty of mapping AI algorithms…