most citedSense: Model Hardware Co-design for Accelerating Sparse CNN on Systolic Array

1 citations · 1 across the 2 of their papers we have counts for

collaborators

2 papers

cs.AR2023

Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity

Wenhao Sun, Zhiwei Zou, Deng Liu +3

Bit-serial architectures can handle Neural Networks (NNs) with different weight precisions, achieving higher resource efficiency compared with bit-parallel architectures. Besides,…

cs.AR2022★ 1 cited

Sense: Model Hardware Co-design for Accelerating Sparse CNN on Systolic Array

Wenhao Sun, Deng Liu, Zhiwei Zou +3

Sparsity is an intrinsic property of convolutional neural network(CNN) and worth exploiting for CNN accelerators, but extra processing comes with hardware overhead, causing many ar…