328 citations · 1.2k across the 57 of their papers we have counts for
8 papers · 1 filter
Reuse Kernels or Activations? A Flexible Dataflow for Low-latency Spectral CNN Acceleration
Yue Niu, Rajgopal Kannan, Ajitesh Srivastava +1
Spectral-domain CNNs have been shown to be more efficient than traditional spatial CNNs in terms of reducing computation complexity. However they come with a `kernel explosion' pro…
Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration
Paul Chen, Pavan Manjunath, Sasindu Wijeratne +2
Graph Neural Networks (GNNs) have revolutionized many Machine Learning (ML) applications, such as social network analysis, bioinformatics, etc. GNN inference can be accelerated by…
Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGA
Bingyi Zhang, Rajgopal Kannan, Viktor Prasanna +1
Synthetic aperture radar (SAR) automatic target recognition (ATR) is the key technique for remote-sensing image recognition. The state-of-the-art convolutional neural networks (CNN…
TransforMAP: Transformer for Memory Access Prediction
Pengmiao Zhang, Ajitesh Srivastava, Anant V. Nori +2
Data Prefetching is a technique that can hide memory latency by fetching data before it is needed by a program. Prefetching relies on accurate memory access prediction, to which ta…
Fine-Grained Address Segmentation for Attention-Based Variable-Degree Prefetching
Pengmiao Zhang, Ajitesh Srivastava, Anant V. Nori +2
Machine learning algorithms have shown potential to improve prefetching performance by accurately predicting future memory accesses. Existing approaches are based on the modeling o…
Model-Architecture Co-Design for High Performance Temporal GNN Inference on FPGA
Hongkuan Zhou, Bingyi Zhang, Rajgopal Kannan +2
Temporal Graph Neural Networks (TGNNs) are powerful models to capture temporal, structural, and contextual information on temporal graphs. The generated temporal node embeddings ou…
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA
Sasindu Wijeratne, Rajgopal Kannan, Viktor Prasanna
Tensor decomposition has become an essential tool in many applications in various domains, including machine learning. Sparse Matricized Tensor Times Khatri-Rao Product (MTTKRP) is…
Programmable FPGA-based Memory Controller
Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen +2
Even with generational improvements in DRAM technology, memory access latency still remains the major bottleneck for application accelerators, primarily due to limitations in memor…