1 citations · 2 across the 2 of their papers we have counts for
2 papers
cs.AR2023★ 1 cited
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information
Aparajithan Nathamuni-Venkatesan, Ram-Venkat Narayanan, Kishore Pula +2
Reverse engineering of FPGA based designs from the flattened LUT level netlist to high level RTL helps in verification of the design or in understanding legacy designs. We focus on…
cs.AR2023★ 1 cited
Reverse Engineering Word-Level Models from Look-Up Table Netlists
Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula +2
Reverse engineering of FPGA designs from bitstreams to RTL models aids in understanding the high level functionality of the design and for validating and reconstructing legacy desi…