3 papers
cs.CR2026
Secure eFPGA-Enabled Edge LLM Inference: Architectural and Hardware Countermeasures
Voktho Das, M Zafir Sadik Khan, Jafar Vafaei +2
Edge deployment of transformer-based models increasingly relies on ASIC accelerators due to their high performance and energy efficiency, achieved through optimized dataflows, spec…
cs.AR2026
Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation
M Zafir Sadik Khan, Kimia Azar, Hadi Kamali
In last two years, large language models (LLMs) have shown strong capabilities in code generation, including hardware design at register-transfer level (RTL). While their use in hi…
cs.PL2025
SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
M Zafir Sadik Khan, Nowfel Mashnoor, Mohammad Akyash +2
In today's rapidly evolving field of electronic design automation (EDA), the complexity of hardware designs is increasing, necessitating more sophisticated automation solutions. Hi…