1 citations · 1 across the 2 of their papers we have counts for
3 papers
cs.CR2023
New Covert and Side Channels Based on Retirement
Ke Xu, Ming Tang, Quancheng Wang +1
Intel processors utilize the retirement to orderly retire the micro-ops that have been executed out of order. To enhance retirement utilization, the retirement is dynamically share…
cs.CR2023★ 1 cited
BandwidthBreach: Unleashing Covert and Side Channels through Cache Bandwidth Exploitation
Han Wang, Ming Tang, Ke Xu +1
In the modern CPU architecture, enhancements such as the Line Fill Buffer (LFB) and Super Queue (SQ), which are designed to track pending cache requests, have significantly boosted…
cs.CR2023
BackCache: Mitigating Contention-Based Cache Timing Attacks by Hiding Cache Line Evictions
Quancheng Wang, Xige Zhang, Han Wang +2
Caches are used to reduce the speed differential between the CPU and memory to improve the performance of modern processors. However, attackers can use contention-based cache timin…