1 citations · 2 across the 5 of their papers we have counts for
5 papers
High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)
Saeideh Nabipour, Javad Javidan
The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of lo…
Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes
Saeideh Nabipour, Javad Javidan
The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable da…
Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code
Saeideh Nabipour, Javad Javidan, Gholamreza Zare Fatin
The finite field multiplier is mainly used in many of today's state of the art digital systems and its hardware implementation for bit parallel operation may require millions of lo…
An Efficient Digital Watermarking Algorithm Based on DCT and BCH Error Correcting Code
Saeideh Nabipour, Javad Javidan, Majid Khorrami +1
Watermarking is a technique for hiding of data in a medium coverage so that its presence is not detectable by a human eye and is recoverable only by the authorized recipient. Two o…
Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)
Saeideh Nabipour, Gholamreza Zare Fatin, Javad Javidan
Finite field multiplier is mainly used in error-correcting codes and signal processing. Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications…