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Rakesh Resalayyan

1 paper hereh-index 7156 citations25 works total

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  • middle author1

Across the 1 of 1 paper where every author was matched, so the position is known.

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  • eess.SY1

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most citedDead-time Compensation Method for Bus-clamping Modulated Voltage Source Inverter

3 citations · 3 across the 1 of their papers we have counts for

collaborators

1 paper

eess.SY2023★ 3 cited

Dead-time Compensation Method for Bus-clamping Modulated Voltage Source Inverter

Reza Asrar Ghaderloo, Yidi Shen, Chanaka Singhabahu +2

Bus-clamping Pulse Width Modulation (PWM) is an effective method to reduce the switching loss in a three-phase voltage source inverter (VSI). In bus-clamping PWM scheme, the phase…

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Not affiliated with arXiv. Researcher data from Semantic Scholar (ODC-BY) and OpenAlex.