5 papers
AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning
Chongxiao Li, Pengwei Jin, Di Huang +14
Performance, power, and area (PPA) optimization is a fundamental task in RTL design, requiring a precise understanding of circuit functionality and the relationship between circuit…
Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction
Jiaping Tang, Jianan Mu, Tianyun Ma +3
Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bu…
RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning
Xinyu Zhang, Zhiteng Chao, Yonghao Wang +6
Register Transfer Level (RTL) design translates high-level specifications into hardware using HDLs such as Verilog. Although LLM-based RTL generation is promising, the scarcity of…
CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization
Yang Zhao, Di Huang, Chongxiao Li +14
The design flow of processors, particularly in hardware description languages (HDL) like Verilog and Chisel, is complex and costly. While recent advances in large language models (…
AGON: Automated Design Framework for Customizing Processors from ISA Documents
Chongxiao Li, Di Huang, Pengwei Jin +12
Customized processors are attractive solutions for vast domain-specific applications due to their high energy efficiency. However, designing a processor in traditional flows is tim…