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20242026
most citedQiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation

1 citations · 1 across the 5 of their papers we have counts for

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cs.CL2026

QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis

Yutong Wu, Chenrui Cao, Pengwei Jin +6

SystemVerilog Assertions (SVAs) are crucial for hardware verification. Recent studies leverage general-purpose LLMs to translate natural language properties to SVAs (NL2SVA), but t…