2 papers
cs.AR2026
Exploring the Efficiency of 3D-Stacked AI Chip Architecture for LLM Inference with Voxel
Yiqi Liu, Noelle Crawford, Michael Wang +2
To overcome the well-known memory bottleneck of AI chips, 3D stacked architectures that employ advanced packaging technology with high-density through-silicon vias (TSVs) pins have…
cs.AR2025
ELK: Exploring the Efficiency of Inter-core Connected AI Chips with Deep Learning Compiler Techniques
Yiqi Liu, Yuqi Xue, Noelle Crawford +2
To meet the increasing demand of deep learning (DL) models, AI chips are employing both off-chip memory (e.g., HBM) and high-bandwidth low-latency interconnect for direct inter-cor…