Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL

Sajjad Ahmed, Alexander Kropotov, Roberto Ignacio Genovese +21

The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, w…