2 papers
cs.AR2026
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Sajjad Ahmed, Alexander Kropotov, Roberto Ignacio Genovese +21
The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, w…
cs.AR2025
TuRTLe: A Unified Evaluation of LLMs for RTL Generation
Dario Garcia-Gasulla, Gokcen Kestor, Emanuele Parisi +6
The rapid advancements in LLMs have driven the adoption of generative AI in various domains, including Electronic Design Automation (EDA). Unlike traditional software development,…