12 citations · 14 across the 2 of their papers we have counts for
2 papers
cs.AR2023★ 12 cited
Evaluating the Efficiency of Software-only Techniques to Detect SEU and SET in Microprocessors
Jose Rodrigo Azambuja, Fernando Sousa, Lucas Rosa +1
This paper presents a detailed evaluation of the efficiency of software-only techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and imple…
cs.AR2007★ 2 cited
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
F. Lima Kastensmidt, L. Sterpone, L. Carro +1
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by…