6 papers
RuC: HDL-Agnostic Rule Completion Benchmark Generation
Arnau Ayguadé Domingo, Miquel Alberti-Binimelis, Cristian Gutierrez-Gomez +5
Large Language Models (LLMs) have rapidly improved in performance across code-related tasks, making their integration into Register Transfer Level (RTL) development increasingly at…
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Sajjad Ahmed, Alexander Kropotov, Roberto Ignacio Genovese +21
The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, w…
EMiX: Emulating Beyond Single-FPGA Limits
Alexander Kropotov, Miquel Moreto, Behzad Salami
FPGA-level emulation is a key step in pre-silicon chip design validation. However, emulating large-scale multi-core systems increasingly exceed the hardware resource capacity of a…
NotSoTiny: A Large, Living Benchmark for RTL Code Generation
Razine Moundir Ghorab, Emanuele Parisi, Cristian Gutierrez +4
LLMs have shown early promise in generating RTL code, yet evaluating their capabilities in realistic setups remains a challenge. So far, RTL benchmarks have been limited in scale,…
TuRTLe: A Unified Evaluation of LLMs for RTL Generation
Dario Garcia-Gasulla, Gokcen Kestor, Emanuele Parisi +6
The rapid advancements in LLMs have driven the adoption of generative AI in various domains, including Electronic Design Automation (EDA). Unlike traditional software development,…
Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication
Mohammadreza Esmali Nojehdeh, Hossein Mokhtarnia, Julian Pavon Rivera +7
This study presents the Cartesian Accumulative Matrix Pipeline (CAMP) architecture, a novel approach designed to enhance matrix multiplication in Vector Architectures (VAs) and Sin…