2 papers
cs.AR2026
HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
Chang-Chih Meng, Yu-Ren Lu, Guan-Yu Lin +3
Integrated Circuit (IC) verification consumes nearly 70% of the IC development cycle, and recent research leverages Large Language Models (LLMs) to automatically generate testbench…
cs.CR2025
CourtGuard: A Local, Multiagent Prompt Injection Classifier
Isaac Wu, Michael Maslowski
As large language models (LLMs) become integrated into various sensitive applications, prompt injection, the use of prompting to induce harmful behaviors from LLMs, poses an ever i…