6 papers
The Turbo-Charged Mapper: Fast and Optimal Mapping for Energy-efficient and Low-latency Accelerator Design
Michael Gilbert, Tanner Andrulis, Vivienne Sze +1
The energy and latency of an accelerator running a deep neural network (DNN) depend on how the computation and data movement are scheduled in the accelerator (i.e., mapping), and p…
Fast and Fusiest: An Optimal Fusion-Aware Mapper for Accelerator Design
Tanner Andrulis, Michael Gilbert, Vivienne Sze +1
A low-latency and energy-efficient tensor algebra accelerator design must optimize how data movement and operations are scheduled (i.e., mapped) in the accelerator architecture. A…
LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space
Michael Gilbert, Yannan Nellie Wu, Joel S. Emer +1
Latency and energy consumption are key metrics in the performance of deep neural network (DNN) accelerators. A significant factor contributing to latency and energy is data transfe…
CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool
Tanner Andrulis, Joel S. Emer, Vivienne Sze
Compute-In-Memory (CiM) is a promising solution to accelerate Deep Neural Networks (DNNs) as it can avoid energy-intensive DNN weight movement and use memory arrays to perform low-…
Architecture-Level Modeling of Photonic Deep Neural Network Accelerators
Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M. Suriyakumar +2
Photonics is a promising technology to accelerate Deep Neural Networks as it can use optical interconnects to reduce data movement energy and it enables low-energy, high-throughput…
Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design
Tanner Andrulis, Ruicong Chen, Hae-Seung Lee +2
Analog Compute-in-Memory (CiM) accelerators use analog-digital converters (ADCs) to read the analog values that they compute. ADCs can consume significant energy and area, so archi…