7 papers
CARMEN: CORDIC-Accelerated Resource-Efficient Multi-Precision Inference Engine for Deep Learning
Sonu Kumar, Mukul Lokhande, Santosh Kumar Vishvakarma +1
This paper presents CARMEN, a runtime-adaptive, CORDIC-accelerated multi-precision vector engine for resource-efficient deep learning inference. The key insight is that CORDIC iter…
EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration
Mukul Lokhande, Ratko Pilipovic, Omkar Kokane +2
Advanced driver-assistance systems (ADAS) require neural compute engines that deliver low-latency inference under strict power and area constraints. Posit arithmetic is attractive…
SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency
Sonu Kumar, Lavanya Vinnakota, Mukul Lokhande +2
The growing demand for edge-AI systems requires arithmetic units that balance numerical precision, energy efficiency, and compact hardware while supporting diverse formats. Posit a…
PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator
Yuval Harary, Almog Sharoni, Esteban Garzón +3
Binary Neural Networks (BNNs), where weights and activations are constrained to binary values (+1, -1), are a highly efficient alternative to traditional neural networks. Unfortuna…
Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation
Mukul Lokhande, Tanushree Dewangan, Mohd Sharik Mansoori +5
This paper introduces Bhasha-Rupantarika, a light and efficient multilingual translation system tailored through algorithm-hardware codesign for resource-limited settings. The meth…
Retrospective: A CORDIC Based Configurable Activation Function for NN Applications
Omkar Kokane, Gopal Raut, Salim Ullah +4
A CORDIC-based configuration for the design of Activation Functions (AF) was previously suggested to accelerate ASIC hardware design for resource-constrained systems by providing f…