4 papers
Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling
Yinrong Li, Zexin Fu, Yichao Zhang +5
Modern large language model workloads put increasing demands on parallel compute capability and on-chip memory capacity, while also stressing fine-grained data movement and synchro…
TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters
Yichao Zhang, Zexin Fu, Tim Fischer +3
A key challenge in on-chip interconnect design is to scale up bandwidth while maintaining low latency and high area efficiency. 2D-meshes scale with low wiring area and congestion…
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi +4
Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO…
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart +11
Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on t…