2 papers
cs.LO2024
TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
Yufeng Li, Yiwei Ci, Qiusong Yang
Design verification is a complex and costly task, especially for large and intricate processor projects. Formal verification techniques provide advantages by thoroughly examining d…
cs.SE2024
SEPE-SQED: Symbolic Quick Error Detection by Semantically Equivalent Program Execution
Yufeng Li, Qiusong Yang, Yiwei Ci +1
Symbolic quick error detection (SQED) has greatly improved efficiency in formal chip verification. However, it has a limitation in detecting single-instruction bugs due to its reli…