2 papers
cs.AR2024
Hypervisor Extension for a RISC-V Processor
Jaume Gauchola, JuanJosé Costa, Enric Morancho +8
This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief expla…
cs.AR2024
Floating Point HUB Adder for RISC-V Sargantana Processor
Gerardo Bandera, Javier Salamero, Miquel Moreto +1
HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is an open-source ISA that many companie…