15 citations · 17 across the 3 of their papers we have counts for
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cs.AR2024
CIS: Composable Instruction Set for Data Streaming Applications
Yu Yang, Jordi Altayó González, Paul Delestrac +1
The enhanced efficiency of hardware accelerators, including Single Instruction Multiple Data (SIMD) architectures and Coarse-Grained Reconfigurable Architectures (CGRAs), is drivin…
cs.AR2022★ 2 cited
Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style
Yu Yang, Ahmed Hemani
High-level synthesis (HLS) has been researched for decades and is still limited to fast FPGA prototyping and algorithmic RTL generation. A feasible end-to-end system-level synthesi…