2 papers
cs.AR2026
TPCS: A Cycle-Level Simulation Paradigm with Native Execution Semantics for RTL Modeling and Generation
Chengzhen Meng, Xiaoyu Li, Chen Bai +2
The growing diversity of domain-specific architectures and microarchitectural designs demands fast and accurate evaluation methods during early design stages. However, existing app…
cs.AR2025
FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation
Chengzhen Meng, Xiuzhuang Chen, Bingcai Sui +3
The rapid advancement of AI workloads and domain-specific architectures has led to increasingly diverse processor microarchitectures, whose design exploration requires fast and acc…