collaborators

12 papers

cs.CR2026

LLM-Assisted Detection and Repair of Hardware Security Vulnerabilities in Verilog Designs

Ethen Santana, Gabriel Gyaase, Hao Zheng

Hardware designs, like software, are susceptible to bugs that can introduce security vulnerabilities and create opportunities for malicious exploitation. Unlike software vulnerabil…

cs.AR2026

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs

Xiangfei Kong, Tasnim Tabassum, Marwan Abdelwahab +1

Large language models can generate register-transfer-level (RTL) designs directly from natural language specifications. Their failures, however, arise mostly from understanding rat…

cs.CL2026

FinHarness: An Inline Lifecycle Safety Harness for Finance LLM Agents

Haoxuan Jia, Yang Liu, Bin Chong +10

Finance LLM agents must simultaneously block prompt-induced unauthorized actions and approve legitimate multi-step business workflows. However, boundary filters often miss irrevers…

cs.CL2026

MAIGO: Mitigating Lost-in-Conversation with History-Cleaned On-Policy Self-Distillation

Haoyu Zheng, Yun Zhu, Shu Yuan +5

Large language models often solve tasks from a fully specified prompt but degrade when the same requirements unfold over multiple turns, known as the lost-in-conversation (LiC) gap…

cs.AI2026

SpecAlign: A Semantic Alignment Framework for SystemVerilog Assertion Generation

Jaime Rafael Imperial, Hao Zheng

Existing Large Language Model (LLM) approaches to SystemVerilog Assertion (SVA) generation primarily focus on syntactic validity and formal verification outcomes, while semantic al…

cs.AI2026

Hallucination as Exploit: Evidence-Carrying Multimodal Agents

Guijia Zhang, Hao Zheng, Harry Yang

Multimodal agents increasingly choose tool calls from screenshots, documents, and webpages, where a false perceptual claim can turn hallucination from an answer-quality error into…