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cs.AR2025
ATHEENA: A Toolflow for Hardware Early-Exit Network Automation
Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides
The continued need for improvements in accuracy, throughput, and efficiency of Deep Neural Networks has resulted in a multitude of methods that make the most of custom architecture…
cs.AR2024
NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
Marta Andronic, George A. Constantinides
Field-Programmable Gate Array (FPGA) accelerators have proven successful in handling latency- and resource-critical deep neural network (DNN) inference tasks. Among the most comput…
cs.AR2024
Exploring FPGA designs for MX and beyond
Ebby Samson, Naveen Mellempudi, Wayne Luk +1
A number of companies recently worked together to release the new Open Compute Project MX standard for low-precision computation, aimed at efficient neural network implementation.…