37 citations · 54 across the 5 of their papers we have counts for
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Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format
Himanshu Thapliyal, Hamid R. Arabnia, M. B Srinivas
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Firstly, this paper proposes no…
Novel Reversible Multiplier Architecture Using Reversible TSG Gate
Himanshu Thapliyal, M. B Srinivas
In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The…
An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates
Himanshu Thapliyal, M. B Srinivas
In recent years, reversible logic has emerged as a promising computing paradigm having its applications in low power computing, quantum computing, nanotechnology, optical computing…
A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits
Himanshu Thapliyal, M. B Srinivas
In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The…
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
Himanshu Thapliyal, Saurabh Kotiyal, M. B Srinivas
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel B…