3 papers
cs.AR2026
Cerberus: Cross-Layer ECC Co-Design for Robust and Efficient Memory Protection
Junhwan Kim, Seunghyun Kim, Yesin Ryu +2
As DRAM scales to higher density and I/O speeds, ensuring data correctness becomes increasingly difficult. Industry has responded with a three-layer stack: on-die ECC (O-ECC), link…
cs.NI2025
Scaling Out Chip Interconnect Networks with Implicit Sequence Numbers
Giyong Jung, Saeid Gorgin, John Kim +1
As AI models outpace the capabilities of single processors, interconnects across chips have become a critical enabler for scalable computing. These processors exchange massive amou…
cs.AR2025
DSLR-CNN: Efficient CNN Acceleration using Digit-Serial Left-to-Right Arithmetic
Malik Zohaib Nisar, Muhammad Sohail Ibrahim, Saeid Gorgin +2
Digit-serial arithmetic has emerged as a viable approach for designing hardware accelerators, reducing interconnections, area utilization, and power consumption. However, conventio…