3 papers
cs.AR2026
CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support
Jingqun Zhang, Maohua Nie, Jiayi Wang +4
Wider vector/SIMD lanes multiply compute throughput, but cache improvements remain challenging. We identify L1 data cache capacity as the most impactful parameter for performance a…
cs.AR2026
HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification
Maohua Nie, Jiang Zhu, Jingqun Zhang +5
We present HierSVA, an integrated suite that combines a pipeline, dataset, and benchmark for LLM-driven hierarchical hardware formal verification. HierSVA-SP pairs an RTL preproces…
cs.AR2026
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines
Jiayi Wang, Maohua Nie, Sin-Chen Lin +2
Commercial FPGAs, such as AMD Versal devices, increasingly incorporate AI engines that exploit low-precision packed-SIMD fused multiply-accumulate (FMA) to achieve proportional thr…