2 papers
cs.PL2026
Specifying Hardware Communication as Programs
Ernest Ng, Nikil Shyamsunder, Francis Pham +2
To test and debug hardware modules, it is common to write two programs: a driver, which translates high-level transactions into interactions on the module's input and output signal…
cs.LO2022
UCLID5: Multi-Modal Formal Modeling, Verification, and Synthesis
Elizabeth Polgreen, Kevin Cheang, Pranav Gaddamadugu +6
UCLID5 is a tool for the multi-modal formal modeling, verification, and synthesis of systems. It enables one to tackle verification problems for heterogeneous systems such as combi…