8 papers
Spiker-LL: An Energy-Efficient FPGA Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks
Alessio Caviglia, Filippo Marostica, Alessandro Savino +1
Deploying adaptive intelligence at the edge remains challenging due to the high computational and energy cost of training neural models. Spiking Neural Networks (SNNs) offer a prom…
Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide
Behnam Farnaghinejad, Antonio Porsia, Annachiara Ruospo +3
Security in modern RISC-V processors demands more than functional correctness: It requires resilience to side-channel attacks. This paper evaluates the vulnerability of the side ch…
CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
Franco Oberti, Stefano Di Carlo, Alessandro Savino
The Controller Area Network (CAN) protocol, essential for automotive embedded systems, lacks inherent security features, making it vulnerable to cyber threats, especially with the…
SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST
Alessio Caviglia, Filippo Marostica, Alessio Carpegna +2
Hardware accelerators are essential for achieving low-latency, energy-efficient inference in edge applications like image recognition. Spiking Neural Networks (SNNs) are particular…
Security and RAS in the Computing Continuum
Martà Alonso, David Andreu, Ramon Canal +10
Security and RAS are two non-functional requirements under focus for current systems developed for the computing continuum. Due to the increased number of interconnected computer s…
Hardware-based stack buffer overflow attack detection on RISC-V architectures
Cristiano Pegoraro Chenet, Ziteng Zhang, Alessandro Savino +1
This work evaluates how well hardware-based approaches detect stack buffer overflow (SBO) attacks in RISC-V systems. We conducted simulations on the PULP platform and examined micr…