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cs.AR2026
DiffRouter: A Differentiable Routing Framework for UltraScale FPGAs
Xiaohan Gao, Zhili Xiong, Yusu Wang +1
Routing has become a major bottleneck in large-scale FPGA design flows, where traditional routers rely on sequential net-by-net processing and rip-up-reroute heuristics. This inher…
cs.AI2026
Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement
Bingyang Liu, Ziming Wei, Xiaohan Gao +1
Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement. Although end-to-end layout generators accelerate initial placement an…
cs.AR2026
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
Haoyi Zhang, Weijian Fan, Xiaohan Gao +3
Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation. In this work…